Chip Design

Total Design Solution

ASIC Biz. Overview

Role of Level 0

  • Top Integration

    - Top Module Design/Verification
    - Customer IP Integration
    - Pad (PWR/GND/Normal) Insertion
    - Clock/Reset Controller Design

  • Test Firmware Suite

    - CortexA8, CortexA7, ARM11, ARM926...
    - PrimeCell Peripherals
    - USB, Ethernet, SD/MMC ...
    - Reusable C Test Code

  • Bus Architecture Design

    - AMBA NIC301, NIC400
    - SONIC SGN
    - Bus Performance Estimation
      (Virtual Bus Master/Slave, Bus Monitor)

  • Test Firmware Suite

    - CortexA8, CortexA7, ARM11, ARM926...
    - PrimeCell Peripherals
    - USB, Ethernet, SD/MMC ...
    - Reusable C Test Code

  • IP Block Design/Verification

    - Algorithm to RTL Design
    - Functional Simulation
    - Code Coverage
    - Spyglass Lint / CDC Check

  • FPGA System Design/Emulation

    - Xilinx Vertex5/6/7
    - FPGA to FPGA Interface Bridge Design
    - Very Large Design : 5 Virtex7 FPGA System
    - DDR3, USB2.0, GMAC, SDMMC Interface

Our Strengths

技术现状

  • Full Chip Design (产品企划及设计)

    · System Architecture Analysis
    · Power Management Control
    · Real Emulation with FPGA

  • Front-End Design (电路合成及分析)

    · Synthesis & Timing Closure
    · DFT(SCAN/BIST/JTAG)
    · STA(Static Timing Analysis)

  • Back-End Design (Auto布局)

    · Full Chip Floor Plan
    · Hierarchical Physical Layout
    · NMOS/PMOS Power Gating

  • Custom Layout (Manual电路布局)

    · ESD Robust I/O Design
    · Special Analog IP Design
    · High Speed Data Path Design

  • Mass Production (量产)

    · Test Vector Generation
    · Yield Improvement
    · Product Reliability Guarantee

  • Field Application (实装以及客户支援)

    · Field Application Analysis
    · Board Level Emulation
    · ESD/EMI Robust Analysis

持有技术现状 (Cont’)